delay fault

英 [dɪˈleɪ fɔːlt] 美 [dɪˈleɪ fɔːlt]

延迟故障

计算机



双语例句

  1. Installed with current overload protector, high& low-pressure switch, electronic timer delay, fault display system.
    具有电流过载保护、高低压制及电子时间延迟等完备的安全保护装置、异常指示系统。
  2. Study on Data of Deliver Delay and Graph fault tolerance diameter of Interconnection networks
    互联网络数据传输延迟与图的容错直径之研究
  3. Delay Fault Test in Boundary Scan and Scan Path Architectures
    扫描与边界扫描电路延迟故障的测试
  4. This dissertation also introduces a novel method of delay testing with variable double observations presented by the author, after summarizing the main methods of delay testing systematically. And a new approach to delay fault diagnosis based on the method is proposed.
    在IC时延测试方面,本文在全面地总结各种通路时延测试方法的基础上,重点介绍了作者提出的可变双观测点的时延测试方法,并基于该方法提出了新的时延故障诊断方法。
  5. At present the commonly used fault models mainly consist of stuck-at fault, stuck-open fault, bridge fault, store fault, delay fault, etc.
    目前常用的故障模型主要有:固定故障,开路故障,桥接故障,存储故障,时滞故障等。
  6. A Test Generation Method for Delay Fault Based on I_ ( DDT) Test
    一种基于IDDT的延时故障测试产生方法
  7. In addition, appropriate current testing methods for delay fault which is hard to detect are also discussed.
    此外,针对较难检测的延迟故障,专门讨论了适合于延迟故障检测的电流测试方法。
  8. Analysis of the Ignition Delay Fault of Solid Rocket Motor Based on FTA
    基于FTA的某发动机点火延迟分析
  9. This paper presents an approach to delay testing with duplicating variable observation points, which provides a high path delay fault coverage by testing a small number of paths.
    本文提供了一种使用双倍可变观测点进行时滞测试的方法,保证了只需要测试少量通路就能完成整个电路的时滞测试。
  10. VLSI Path Delay Fault Test Method Based on Electron Beam Probe Technology
    基于电子束探测技术的VLSI路径延时故障测试方法
  11. However, it is found that there are untestable path delay faults in ETG PLA under path delay fault model.
    在基于通路时滞故障模型的分析中,发现ETGPLA中存在通路时滞故障既不是强键可测的,也不是有效非强键可测的。
  12. And a new approach to delay fault diagnosis based on the method is proposed.
    基于该方法提出了新的时延故障诊断方法,实现和完善了可变双观测点的时延测试系统DTwDO。
  13. BIST-Based Delay-Fault Testing of FPGA Device
    基于BIST的带时延故障的FPGA测试
  14. The algorithm uses three patterns to activate delay fault.
    该算法利用3个向量来激活延时故障。
  15. Measurement based delay fault diagnosis
    基于测量的时延故障诊断
  16. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.
    实验表明,这种功能测试集具有实现低路径延迟故障覆盖范围的功能。
  17. The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
    研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
  18. First, the thesis analyzes the delay fault testability of ETG PLA, which is a kind of two-level circuit with test generation complexity being linear to the number of products.
    首先从特殊的两级电路,ETGPLA,着手进行可测试性分析。ETGPLA是一种逻辑功能测试向量产生复杂度与乘积线数成正比的两级电路。
  19. The single transition on the output of a target path can be helpful to delay fault diagnosis.
    利用单跳变敏化在目标通路的原始输出线上输出单跳变的特点,可以进行时延故障诊断。
  20. By modeling the distribution network, calculate the maximum delay time of fault detection, educe the requirement of sample frequency.
    通过对配网线路建模计算故障检测最大延迟时间,据此得到了对装置采样频率的要求。
  21. Based on exploitation of design tendency to be hierarchical and modular for modern arithmetic circuits, a satisfiability-based path delay test scheme is proposed. In such scheme, a hierarchical path delay fault test method and a modular functional delay fault test method are researched respectively.
    针对当今算术运算电路具有层次化、模块化的结构设计特点,本文以通路时延故障模型为基础,研究了采用布尔可满足性的层次化通路和模块化功能的时延故障测试方法。
  22. Include that sufficiently consider the time-variant delay, network fault and external disturbance in modeling of networked control system.
    包括在网络化控制系统的建模中,应更加充分考虑到时变延迟、故障和外部扰动等因素的影响。
  23. As a key technology of Noc, it plays an important role in the performance of the network, such as throughput, delay, fault tolerance and load balance.
    作为片上网络的关键技术之一,它对整个网络的吞吐、时延、容错能力以及负载均衡等性能具有至关重要的影响。
  24. Evaluating a routing protocol mainly bases on network life cycle, transmission delay, routing fault tolerance capability, routing safety and expansibility.
    评价无线传感器网络路由协议的性能指标主要有网络生命周期、传输延迟时间、路径容错能力、路由的安全和网络的可扩展性等。
  25. In the past, much attention has been paid to stuck-at fault test and little research has been reported on the delay fault test for these circuits.
    过去对这类电路的故障测试集中于呆滞型故障,对其时延故障的测试少有报道。
  26. The proposed scheme is well balanced between the fault coverage and the number of test patterns. Simulation results show the scheme has merit of high delay fault coverage with low hardware cost and small number of test. 4.
    本文方案在测试故障覆盖率和测试向量数之间做到了良好的兼顾,仿真结果表明这样的方法具有硬件成本低、测试序列少且又具有较高的故障覆盖率的优点。
  27. The main contentsinclude: First, the delay uncertain nonlinear robust fault tolerant control problem.
    主要研究内容包括:首先,时滞不确定非线性系统的鲁棒容错控制问题。
  28. Delay fault test is researched for arithmetic circuits in this thesis.
    本文研究了算术运算电路的通路时延故障测试。
  29. Such kind of single-input-change sequences has been designated to be more effective than multiple-input-change sequences when highly robust delay fault coverage is targeted.
    这种单跳变序列比多跳变序列更具有通路时延故障测试的强健性。
  30. The path delay fault test of array multipliers is researched.
    研究了乘法器的通路时延故障测试。